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Ge/high-k Gates for Monolithic 3D Integration

Time: Fri 2021-10-22 09.00

Location: Zoom:, Sal C, Kistagången 16, Kista (English)

Subject area: Information and Communication Technology

Doctoral student: Laura Zurauskaite , Elektronik och inbyggda system

Opponent: Dr. Francois Andrieu, CEA - Laboratoire d'Électronique des Technologies de l'Information (LETI), Grenoble, Rhône-Alpes, France

Supervisor: Associate professor Per-Erik Hellström, Elektronik och inbyggda system; Professor Mikael Östling, Elektronik och inbyggda system

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Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation.

In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for Si-cap growth conditions. Selected gate stacks with GeOx and Si-cap passivation have been integrated in Ge pFET process on in-house fabricated germanium on insulator substrates. Subthreshold slope values inline with previous reports have been achieved, as well as 60 % higher hole mobility than in reference silicon on insulator pFETs. Moreover, initial results of Si-cap and TmSiO interfacial layer integration ingermanium on insulator nFETs have been demonstrated.

This work presents both advantages and limitations of each gate stacksolution on Ge platform. The processes employed in this work are monolithic 3D integration compatible, and demonstrate that with some process optimization Ge transistors could be integrated on Si platform in monolithic3D integration fashion.